1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices and to a semiconductor device and, in particular, to a method of manufacturing heterojunction bipolar transistors having reproducible and repeatable device characteristics in a simplified manner while eliminating parasitic components.
2. Discussion of the Background
Heterojunction bipolar transistors are commonly manufactured having a vertical structure. Emitter, collector and base layers are deposited and emitter and collector mesas are formed from the respective layers. Alignment of the collector and emitter mesas is critical to device performance. Other manufacturing methods have attempted to produce vertical HBT devices with aligned emitter and collector regions. This a critical alignment and any manufacturing errors diminishes device performance. Further, these methods do not provide the necessary tolerance to produce a manufacturable HBT having reproducible and repeatable device characteristics necessary for a commercial device.
U.S. Pat. No. 5,318,916 describes a method of symmetric self aligned processing, the disclosure of which is herein incorporated by reference. Symmetric emitter and collector portions are formed using front and back side processing of a wafer. An emitter mesa is etched using an emitter contact or other feature as a mask on the front side of the wafer. The collector layer is formed using back side processing where the substrate is removed to expose the collector layer. A contact is formed on the collector layer symmetrically aligned with the emitter contact. This process is done photolithographically and may be misaligned due to manufacturing tolerances.
The collector layer is etched to produce the collector mesa. The alignment of the collector contact may be improved in the case of very thin layers with an infrared alignment tool. However, the alignment of the emitter and collector is still a critical alignment step and subject to manufacturing tolerances and misalignment. Any misalignment or offset due to the photolithographic or other processing steps will degrade the device characteristics and limit scaling of the device to a minimum feature size.